System-on-chip Design Engineering Manager visa sponsorship salary
Across 2 certified work-visa filings, the median wage for System-on-chip Design Engineering Manager is $237,567. The middle half of filings fall between $217,157 and $257,977, and the top decile begins at $270,223. Classified under SOC 11-9041.00 (Architectural and Engineering Managers).
This is one of many job titles filed under Architectural and Engineering Managers. That page pools every variant, so its figures rest on far more filings than this one.
- Median
- $237,567
- 25th pct
- $217,157
- 75th pct
- $257,977
- 90th pct
- $270,223
- Filings
- 2
Who pays what for System-on-chip Design Engineering Manager
Ranked by number of certified filings
| Employer | Filings | 25th | Median | 75th |
|---|---|---|---|---|
| Intel Corporation | 2 | $217,157 | $237,567 | $257,977 |
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Intel Corporation | Hillsboro, OR | $196,747 | IV | Mar 31, 2025 |
| Intel Corporation | Santa Clara, CA | $278,387 | IV | Feb 18, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.