Sr Principal Fpga/asic Design Engineer visa sponsorship salary
Across 2 certified work-visa filings, the median wage for Sr Principal Fpga/asic Design Engineer is $276,504. The middle half of filings fall between $276,504 and $276,504, and the top decile begins at $276,504. Classified under SOC 17-2199.00 (Engineers, All Other).
This is one of many job titles filed under Mechatronics Engineers. That page pools every variant, so its figures rest on far more filings than this one.
- Median
- $276,504
- 25th pct
- $276,504
- 75th pct
- $276,504
- 90th pct
- $276,504
- Filings
- 2
Who pays what for Sr Principal Fpga/asic Design Engineer
Ranked by number of certified filings
| Employer | Filings | 25th | Median | 75th |
|---|---|---|---|---|
| RED Digital Cinema, Inc. | 2 | $276,504 | $276,504 | $276,504 |
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| RED Digital Cinema, Inc. | Thousand Oaks, CA | $276,504 | IV | Apr 30, 2025 |
| RED Digital Cinema, Inc. | Thousand Oaks, CA | $276,504 | IV | Apr 22, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.