Sr Principal Fpga/asic Design Engineer salary at RED Digital Cinema, Inc.
Based on 2 certified work-visa filings, the median filed wage is $276,504. That is 0% above the $276,504 median across all employers filing this title.
Median
$276,504
25th pct
$276,504
75th pct
$276,504
90th pct
$276,504
Filings
2
Individual filings
Certified determinations for this role
| Location | Wage | Prevailing | Level | Visa | Decided |
|---|---|---|---|---|---|
| Thousand Oaks, CA | $276,504 | $143,645 | IV | H-1B | Apr 30, 2025 |
| Thousand Oaks, CA | $276,504 | $149,282 | IV | H-1B | Apr 22, 2025 |
All roles at RED Digital Cinema, Inc. →
Every job title this employer sponsors
Sr Principal Fpga/asic Design Engineer across all employers →
Market rate for this role
Figures are base salary as filed with the US Department of Labor and exclude bonus and equity. SponsorWage does not provide immigration advice.