Fpga Silicon Design Verification Engineer visa sponsorship salary
Across 4 certified work-visa filings, the median wage for Fpga Silicon Design Verification Engineer is $143,901. The middle half of filings fall between $131,957 and $151,895, and the top decile begins at $151,895. Classified under SOC 17-2072.00 (Electronics Engineers, Except Computer).
This is one of many job titles filed under Electronics Engineers, Except Computer. That page pools every variant, so its figures rest on far more filings than this one.
- Median
- $143,901
- 25th pct
- $131,957
- 75th pct
- $151,895
- 90th pct
- $151,895
- Filings
- 4
Who pays what for Fpga Silicon Design Verification Engineer
Ranked by number of certified filings
| Employer | Filings | 25th | Median | 75th |
|---|---|---|---|---|
| Altera Corporation | 4 | $131,957 | $143,901 | $151,895 |
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Altera Corporation | Austin, TX | $135,907 | III | Jul 28, 2025 |
| Altera Corporation | San Jose, CA | $120,108 | — | Jun 25, 2025 |
| Altera Corporation | San Jose, CA | $151,895 | — | May 15, 2025 |
| Altera Corporation | San Jose, CA | $151,895 | — | Apr 30, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.