Design Verification Principal Engineer visa sponsorship salary
Across 7 certified work-visa filings, the median wage for Design Verification Principal Engineer is $205,000. The middle half of filings fall between $183,500 and $205,000, and the top decile begins at $209,800. Classified under SOC 17-2072.00 (Electronics Engineers, Except Computer).
Median
$205,000
25th pct
$183,500
75th pct
$205,000
90th pct
$209,800
Filings
7
$151,250$217,000
Who pays what for Design Verification Principal Engineer
Ranked by number of certified filings
| Employer | Filings | 25th | Median | 75th |
|---|---|---|---|---|
| Marvell Semiconductor, Inc. | 7 | $183,500 | $205,000 | $205,000 |
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Marvell Semiconductor, Inc. | Austin, TX | $162,000 | IV | Aug 19, 2025 |
| Marvell Semiconductor, Inc. | Santa Clara, CA | $217,000 | IV | Aug 8, 2025 |
| Marvell Semiconductor, Inc. | Santa Clara, CA | $205,000 | IV | Feb 18, 2025 |
| Marvell Semiconductor, Inc. | Santa Clara, CA | $205,000 | IV | Jan 24, 2025 |
| Marvell Semiconductor, Inc. | Santa Clara, CA | $205,000 | IV | Dec 2, 2024 |
| Marvell Semiconductor, Inc. | Santa Clara, CA | $205,000 | IV | Oct 15, 2024 |
| Marvell Semiconductor, Inc. | Westborough, MA | $137,000 | IV | Oct 4, 2024 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.