Technologist, Systems Design Verification Engineering visa sponsorship salary
Across 2 certified work-visa filings, the median wage for Technologist, Systems Design Verification Engineering is $160,638. The middle half of filings fall between $160,638 and $160,638, and the top decile begins at $160,638. Classified under SOC 17-2072.00 (Electronics Engineers, Except Computer).
This is one of many job titles filed under Electronics Engineers, Except Computer. That page pools every variant, so its figures rest on far more filings than this one.
- Median
- $160,638
- 25th pct
- $160,638
- 75th pct
- $160,638
- 90th pct
- $160,638
- Filings
- 2
Who pays what for Technologist, Systems Design Verification Engineering
Ranked by number of certified filings
| Employer | Filings | 25th | Median | 75th |
|---|---|---|---|---|
| Sandisk Technologies, Inc. | 2 | $160,638 | $160,638 | $160,638 |
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Sandisk Technologies, Inc. | Tustin, CA | $160,638 | IV | May 9, 2025 |
| Sandisk Technologies, Inc. | Irvine, CA | $160,638 | IV | May 9, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.