Sr. Sys/test Validation Engineer visa sponsorship salary
Across 1 certified work-visa filings, the median wage for Sr. Sys/test Validation Engineer is $117,382. The middle half of filings fall between $117,382 and $117,382, and the top decile begins at $117,382. Classified under SOC 17-2072.00 (Electronics Engineers, Except Computer).
Median
$117,382
25th pct
$117,382
75th pct
$117,382
90th pct
$117,382
Filings
1
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Advanced Micro Devices, Inc. | Austin, TX | $117,382 | II | Mar 13, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.