Cpu Design Timing Engineer visa sponsorship salary
Across 1 certified work-visa filings, the median wage for Cpu Design Timing Engineer is $153,929. The middle half of filings fall between $153,929 and $153,929, and the top decile begins at $153,929. Classified under SOC 17-2072.00 (Electronics Engineers, Except Computer).
Median
$153,929
25th pct
$153,929
75th pct
$153,929
90th pct
$153,929
Filings
1
Individual filings
Most recent certified determinations
| Employer | Location | Wage | Level | Decided |
|---|---|---|---|---|
| Apple Inc. | Santa Clara, CA | $153,929 | — | Sep 5, 2025 |
Prevailing wage levels I through IV reflect the experience and responsibility the employer attested to, not seniority titles. A level I filing is an entry-level determination; level IV is fully competent and independent. Comparing across levels explains much of the spread between the 25th and 90th percentile above.