Design Verification Engineer salary at Astera Labs, Inc.
Based on 2 certified work-visa filings, the median filed wage is $140,000. That is 8% below the $151,433 median across all employers filing this title.
Median
$140,000
25th pct
$140,000
75th pct
$140,000
90th pct
$140,000
Filings
2
How Astera Labs, Inc. compares
Other employers filing Design Verification Engineer
| Employer | Filings | Median | vs. this page |
|---|---|---|---|
| Apple Inc. | 38 | $156,183 | +12% |
| Texas Instruments Incorporated | 13 | $118,500 | -15% |
| Meta Platforms, Inc | 11 | $186,000 | +33% |
| Cirrus Logic International Semiconductor LTD. | 10 | $152,194 | +9% |
| Sivaltech, Inc. | 8 | $150,000 | +7% |
| Enfabrica Corporation | 7 | $235,000 | +68% |
| Fiori Technology Solutions INC | 4 | $97,000 | -31% |
| Edveon, Inc. | 2 | $140,546 | +0% |
| Astera Labs, Inc. | 2 | $140,000 | — |
| AumRaj, Inc. | 2 | $108,000 | -23% |
Individual filings
Certified determinations for this role
| Location | Wage | Prevailing | Level | Visa | Decided |
|---|---|---|---|---|---|
| San Jose, CA | $140,000 | $130,923 | — | H-1B | Jun 17, 2025 |
| San Jose, CA | $140,000 | $127,239 | — | H-1B | Jun 16, 2025 |
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Market rate for this role
Figures are base salary as filed with the US Department of Labor and exclude bonus and equity. SponsorWage does not provide immigration advice.